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For a direct mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. assume a write through cache policy.
tag index offset
31-10 9-5 4-0
1. what is the cache block size (in words)?
2. 151 how many entries does the cache have?
3. 151 cod $5.3> what is the ratio between total bits required for such a cache implementation over the data storage bits?
address
starting from power on, the following byte-addressed cache references are recorded.
0 4 1 132 232 160 3024 30 140 3100 180 2180
4. [10 how many blocks are replaced?
5. what is the hit ratio?
6. list the final state of the cache, with each valid entry represented as a record of sindex, tag, data>

Respuesta :

azikennamdi

From the information given, the cache block size is 32. See explanation below.

How do we arrive at the cache block size?

Where the offset is 5 bits, the block size is given as:

2⁵ = 32.

Hence, the total number of blocks in the cache is 32.

How many entries does the cache have?

Note that

Total cache size = No. of entries (No. of tag bits + data bits + valid bit)

Hence,

= 32 x (22+ 256 +1)

= 8, 928 bits

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